SoC Tile, Part 1: Low Power Island (LP) E-Cores For Efficiency
SoC Tile, Part 1: Low-Power Island E-Cores, Designed for Ultimate Efficiency Diving a little deeper into the SoC tile within Intel's Meteor Lake architecture, Intel hasn't just opted for a minor change but has made a significant leap forward, especially regarding I/O fabric scalability. The SoC tile itself isn't built on Intel 4 like the compute tile but is made by TSMC on their N6 node. Intel has ditched the old limitations of mesh routing by implementing a Network-On-Chip (NOC) on the silicon.
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